1. Field of the Invention
The present invention generally relates to a single pole single throw (SPST) switch, a single pole double throw (SPDT) switch, and a communication apparatus using the SPDT switch and, more particularly, to an SPST switch, an SPDT switch, as an antenna switch of a mobile communication apparatus and a communication apparatus using these switches.
2. Description of the Related Art
With a recent tendency to reduce the power consumption of mobile communication apparatuses, reductions in transmission loss and power consumption are required for an antenna switch.
FIG. 11 shows a circuit diagram of an SPST switch having a basic configuration which is disclosed in Japanese Unexamined Patent Publication No. 9-191268 as a conventional SPST (Single Pole Single Throw) switch (switch for connecting and disconnecting two terminals to each other). In FIG. 11, an SPST switch 1 includes a first terminal 2, a second terminal 3, a diode D1 connected between the first terminal 2 and the second terminal 3, an induction element L1 and a capacitor element C1 which are connected in series with each other and are connected in parallel with the diode D1, and a capacitor element C2 connected in parallel with the diode D1.
In the SPST switch 1 arranged as described above, when a current flows in the diode D1, the diode D1 is equivalent to a resistor having a small resistance (ON resistance), the first terminal 2 and the second terminal 3 are almost directly connected to each other, and the SPST switch 1 is turned on. At this time, the induction element L1 or the capacitor elements C1 and C2 do not adversely affect a signal passing through the SPST switch 1. In contrast, when no current flows in the diode D1, the diode D1 is equivalent to a capacitor element having a small capacitance (OFF capacitance). However, in this case, the diode D1 may resonate at a signal frequency which is a function of the OFF capacitance in parallel with the induction element L1 and the capacitor elements C1 and C2. An impedance between the first terminal 2 and the second terminal 3 becomes almost infinite, and the SPST switch 1 is turned off. In this manner, by controlling whether a current flows in the diode D1 or not, the switch 1 exhibits the characteristics of an SPST switch.
FIG. 12 shows a circuit diagram of an SPST switch having a basic configuration which is disclosed as another conventional SPST switch in Japanese Unexamined Patent Publication No. 9-191268. The same reference numerals as in FIG. 11 denote the same parts or similar parts in FIG. 12, and a detailed description thereof will be omitted. In FIG. 12, an SPST switch 4 is arranged such that a first terminal 2 and a second terminal 3 are connected to each other in series through a diode D2 and an induction element L2, and a capacitor element C3 is connected in parallel to the diode D2 and the induction element L2.
In the SPST switch 4 arranged as described above, when a current flows in the diode D2, the diode D2 can be almost neglected because the diode D2 is equivalent to a resistor having a small resistance (ON resistance). The induction element L2 and the capacitor element C3 are connected in parallel with each other between the first terminal 2 and the second terminal 3. When the values of the induction element L2 and the capacitor element C3 are set such that the induction element L2 and the capacitor element C3 resonate at a signal frequency, an impedance between the first terminal 2 and the second terminal 3 becomes almost infinite, and the SPST switch 4 is turned off. In contrast, when no current flows in the diode D2, the diode D2 is equivalent to a capacitor element having a small capacitance (OFF capacitance) and the impedance of the path through the diode D2 and the induction element L2 between the first terminal 2 and the second terminal 3 is high. However, when the capacitance of the capacitor element C3 is set to be a relatively large value, the impedance of the path through the capacitor element C3 is low, the first terminal 2 and the second terminal 3 are almost directly connected to each other, and the SPST switch 4 is turned on. In this manner, the switch 4 exhibits the characteristics of an SPST switch by controlling whether a current flows in the diode D2 or not. Note that the SPST switch 4 operates in reverse to the SPST switch 1 shown in FIG. 11 by controlling whether a current flows in the diode or not.
FIG. 13 shows a circuit diagram of an SPST switch having a basic configuration which is disclosed as still another conventional SPST switch in Japanese Unexamined Patent Publication No. 7-303001. The same reference numerals as in FIG. 11 denote the same parts or similar parts in FIG. 13, and a detailed description thereof will be omitted. In FIG. 13, an SPST switch 5 is arranged such that an induction element L3 is connected to a first terminal 2 and a second terminal 3, and a drain and a source of a FET Q1 are connected to both terminals of the induction element L3, respectively. In this case, the gate of the FET Q1 is connected to a control terminal 6. In FIG. 13, with respect to the terminals of the FET Q1, a symbol D is added to only the drain, while symbols at the source and the gate are omitted.
In the SPST switch 5 arranged as described above, when the FET Q1 is in an ON state, the source-drain portion of the FET Q1 is equivalent to a resistor having a small resistance (ON resistance). For this reason, the first terminal 2 and the second terminal 3 are almost directly connected to each other through the FET Q1, and the SPST switch 5 is turned on. In contrast, when the FET Q1 is in an OFF state, the source-drain portion of the FET Q1 is equivalent to a capacitor element having a small capacitance (OFF capacitance). In this case, when only the FET Q1 is connected between the first terminal 2 and the second terminal 3, the OFF capacitance of the FET Q1 operates to decrease the impedance between the first terminal 2 and the second terminal 3. However, when the induction element L3 is connected, it may resonate in parallel with the OFF capacitance of the FET Q1 at a signal frequency, the impedance between the first terminal 2 and the second terminal 3 can be made almost infinite, and the SPST switch 5 is turned off. In this manner, when the FET Q1 is turned on or off, the switch 5 exhibits the characteristics of an SPST switch.
When two SPST switches described above are combined with each other, the combination can also be operated as an SPDT (Single Pole Double Throw) switch (switch having three terminals in which one (common) terminal may be connected to either one of the two remaining terminals).
However, in the SPST switch 1 shown in FIG. 11, since the first terminal 2 and the second terminal 3 are connected to each other through the diode D1 when the SPST switch 1 is in an ON state, a transmission loss, although it is small, is disadvantageously generated due to the ON resistance of the diode D1. In the SPST switch 4 shown in FIG. 12, since the first terminal 2 and the second terminal 3 are connected to each other through the capacitor element C3 when the SPST switch 4 is in an ON state, a transmission loss is disadvantageously generated due to the impedance of the capacitor element C3. In any one of the SPST switches 1 and 4, a direct current must continuously flow in the switches 1 or 4 to turn the diode D1 or D2 on, and a relatively large power consumption is disadvantageously required.
Also in the SPST switch 5 shown in FIG. 13, since the first terminal 2 and the second terminal 3 are connected to each other through the FET Q1 when the SPST switch 5 is in an ON state, a transmission loss is disadvantageously generated due to the ON resistance of the FET Q1.
As in an SPDT switch, using the SPST switches described above, the same problems as described above are exhibited.
The present invention has as an object to solve the above problems and to provide: (i) an SPST switch having a small transmission loss and a small power consumption, (ii) an SPDT switch, and (iii) a communication apparatus using the SPDT switch.
In order to solve the above problems, an SPST switch according to an aspect of the present invention includes first and second terminals, a control terminal, a FET, an induction element, and a capacitor element. The drain and the source of the FET are connected to each other in series through the induction element and the capacitor element, one terminal of the capacitor element is connected to the first terminal, the other terminal is connected to the second terminal, the gate of the FET is connected to the control terminal, the capacitance of the capacitor element is made equal to the OFF capacitance of the FET, and the inductance of the induction element is set to be such a value that the induction element resonates at a signal frequency with the capacitor element.
An SPDT switch according to a second aspect of the present invention includes first, second, and third terminals, first and second control terminals, first and second FETs, first and second induction elements, and first and second capacitor elements. The drain and the source of the first FET are connected to each other in series through the first induction element and the first capacitor element, the gate of the first FET is connected to the first control terminal, the capacitance of the first capacitor element is equal to the OFF capacitance of the first FET, and the inductance of the first induction element is set to be such a value that the first induction element resonates at a signal frequency with the first capacitor element. The drain and the source of the second FET are connected to each other in series through the second induction element and the second capacitor element, the gate of the second FET is connected to the second control terminal, the capacitance of the second capacitor element is made equal to the OFF capacitance of the second FET, and the inductance of the second induction element is set to be such a value that the second induction element resonates at a signal frequency with the second capacitor element. One terminal of each of the first and second capacitor elements are connected to each other and to the first terminal, the other terminal of the first capacitor element is connected to the second terminal, and the other terminal of the second capacitor element is connected to the third terminal.
An SPDT switch according to a third aspect of the present invention includes first, second, and third terminals, a control terminal, a FET, an induction element, a capacitor element, and a switch element having two signal terminals and a switching terminal. The switch element is turned on/off to be interlocked with an ON/OFF operation of the FET. The drain and the source of the FET are connected to each other in series through the induction element and the capacitor element, the gate of the FET is connected to the control terminal, the capacitance of the capacitor element is equal to the OFF capacitance of the FET, and the inductance of the induction element is set to be such a value that the induction element resonates at a signal frequency with the capacitor terminal. The switching terminal of the switch element is connected to the control terminal, one terminal of the capacitor element is connected to the first terminal and the other terminal is connected to the second terminal, one of the two signal terminals of the switch element is connected to one terminal of the capacitor element and the other is connected to the third terminal.
With the configuration described above, in an SPST switch and an SPDT switch according to the present invention, a transmission loss and a power consumption can be reduced.
Also in a communication apparatus according to the present invention, reductions in transmission loss and power consumption can be achieved.